Tag Archives: verilog

Memory stuff with verilog

I’m working on a LIFO module for the CPU I’m designing and was wondering whether or not I should use the megafunction for a ram block or just use an array of  regs. I went with an array of regs because that’s simpler. I expected it to just create a pile of FFs but the compiler used some of the on chip SRAM instead. Cool. I’d rather use of some of the M9K blocks than chew up a bunch of LEs  for that.

inferred_ram