Implementing a CPU with verilog

procmap

So far I have a number of device modules put together and wired up on a bus. I’ve also implemented a push down stack as well. I’m getting close towards my goal of putting together a stack based CPU in verilog. The next module I’m going to write will be an instruction fetch / decode block. From there I should be able to start fleshing out some of the opcodes and get it running some code. I still haven’t decided what I want to do regarding interrupts or whether or not I want to support relative jumps. I’ve also come to the conclusion that my original requirement of three or less clocks per machine cycle isn’t going to be feasible for my first design. I’ll be lucky if I can get it down to three with the opcodes that have no immediate.

It’s a 16 bit machine with a 32 bit address bus, 32 instructions and two push down stacks. I’ve started putting together an overview here: http://www.dillo.us/wiki/projects/doku.php?id=fpga_stack_machine .I’m having a lot of fun putting it together and when I get it finished I should have built up enough experience to be able to do something with that USB phy.

W7S5YPWPGPAN

Driving an LCD shutter with a PIC 16F917

lcd_off lcd_on

This is a prototype I put together using an LCD shutter from a 5 dollar novelty keychain. I’m driving the shutter using the built in LCD segment driver on a PIC 16F917. The ultimate goal of this is to investigate the feasibility of adding stereoscopic support to my graphics engine by triggering the LCD with a photo sensor in the corner of the screen. Every even frame would have a light square in the corner and a black square in the odd frames.

The switching response in the LCD seems pretty poor. In the video below I’m strobing it ~18Hz. The red LED on the bread board is switched on when the LCD is dark. In this test the LED shines right through when it should be blocked. I don’t know whether or not the issue is with how the shutter is being driven or if it’s a response time issue. I’ll have to do more testing to figure that out. I don’t have time to move forward with this so I’m going to have to shelve it for now…

Memory stuff with verilog

I’m working on a LIFO module for the CPU I’m designing and was wondering whether or not I should use the megafunction for a ram block or just use an array of  regs. I went with an array of regs because that’s simpler. I expected it to just create a pile of FFs but the compiler used some of the on chip SRAM instead. Cool. I’d rather use of some of the M9K blocks than chew up a bunch of LEs  for that.

inferred_ram

Unhappy capacitors

My 21″ Samsung 204T monitor has been acting up for over a year. On power up it would flicker for a minute or two and eventually even out. This evening it finally died. I popped it open and found two bulging capacitors:

The two bad caps were each 820uF, wired in parallel. I didn’t have any of that size in my parts drawer, so I used a 1000uF, 470uF and 220uF. There was an unused spot for a capacitor next to the two that were bad, so I used that for my third capacitor. I drilled the holes a little wider so I could have room to fit some heat shrink tubing on that third capacitor where it went through the board. Then I soldered in parallel with the rest:

I put everything back together and the monitor came right up without delay and no flicker. The monitor is about 8 years old, maybe I’ll get another 8 years out of it.